1. Field of the Invention
The present invention generally relates to integrated circuits and more particularly to an improved integrated circuit design and method which utilizes voltage islands in application specific integrated circuit (ASIC) designs that make increasing use of power supply switching techniques to control chip power consumption.
2. Description of the Related Art
As technology scales for increased circuit density and performance, the need to reduce power consumption increases in significance as designers strive to utilize the advancing silicon capabilities. The consumer product market further drives the need to minimize chip power consumption.
The total power consumed by conventional CMOS circuitry is composed of two primary sources. The first is active power consumed by circuits as they switch states and either charge or discharge the capacitance associated with the switching nodes. Active power represents the power consumed by the intended work of the circuit to switch signal states and thus execute logic function, This power is not present if the circuit in question is not actively switching. Active power is proportional to the capacitance that is switched, the frequency of operation and to the square of the power supply voltage. Due to technology scaling, the capacitance per unit area increases with each process generation. The power increase represented by this capacitance increase is offset by the scaling of the power supply voltage, Vdd.
The frequency of operation, however, increases with each generation, leading to an overall increase in active power density from technology generation to technology generation. This increasing power density in turn drives the need for more expensive packaging, complex cooling solutions and decreased reliability due to increased temperatures.
Therefore, there is a need for a method and structure that increases performance, while at the same time decreases power consumption. The invention described below satisfies these by providing a solution to the problem of optimum placement of power supply switch circuits.